1. Field of the Invention
The present invention relates to a current source applicable to a controllable delay line and a method for designing the current source.
2. Description of the Related Art
FIG. 1 is a schematic diagram showing a conventional controllable delay line 100. six p-channel metal oxide semiconductor field effect transistors (PMOSFETs) M1-M6 constitute six current branches of the current source 110 of the controllable delay line 100. The input signals a, b, c, d, and e constitute the digital input vector of the current source 110. The digital input vector controls the on/off condition of the PMOSFETs M1-M5, which controls the total output current of the current source 110. The output current of the current source 110 determines the delay of the controllable delay line 100.
The controllable delay line 100 has a small area due to its analog design. As shown in FIG. 2, the delay of the controllable delay line 100 is monotonic in response to different values of the digital input vector abcde. However, due to its binary code control mechanism, the delay of the controllable delay line 100, either derived from empirical equation or obtained from measurement, is non-linear. This non-linearity has an adverse effect on the resolution of the controllable delay line 100.
FIG. 3 is a schematic diagram showing a conventional current-starved controllable delay line 300. The output current of the current source 320 of the controllable delay line 300 is controlled by a thermometer code D0-D6 instead of a binary code. Therefore, a binary-to-thermometer conversion circuit 310 is required to convert the 3-bit binary input code B0-B2 to the 7-bit thermometer code D0-D6. FIG. 4 is a schematic diagram showing the circuit of the current source 320. PMOSFETs MS0-MS7 are always turned on. MS0-MS7 represent the eight current branches of the current source 320. The current branch including the PMOSFET MS0 is always turned on. Each of the other seven current branches of the current source 320 is turned on or turned off in response to one bit of the thermometer code D0-D6.
The delay of the controllable delay line 300 is linear because of its thermometer code control mechanism. The linearity is desirable. However, a current source controlled by thermometer code occupies more area than a current source controlled by binary code does because the current source controlled by thermometer code needs an additional binary-to-thermometer conversion circuit.
FIG. 5 is a schematic diagram showing a conventional programmable digital delay line 500. The digital delay line 500 consists of many stages, such as the stages 510 and 520. Each stage includes a delay unit and a multiplexer. For example, the stage 510 includes the delay unit 511 and the multiplexer 512. The delay unit 511 of the first stage 510 includes two serially connected inverters for delaying the input signal. The delay unit 521 of the second stage 520 includes four serially connected inverters for delaying the input signal, and so on. Finally, the delay unit of the last stage includes 2N+1 serially connected inverters for delaying the input signal. The input code C0-CN determines the transmission path of the input signal through the stages, thus controlling the delay of the digital delay line 500.
The digital delay line 500 features linear delay and simple design. However, such a digital delay line imposes very large area overhead due to the amount of inverters and multiplexers required.